| 摘要 |
PURPOSE:To impress voltage without erroneous writing or erasing by a method wherein, after impressing a specified node with power supply voltage, multiple nodes are impressed with high voltage in a 5V single power supply EEPROM. CONSTITUTION:A voltage impressing circuit is composed by means of connecting an MNOS element comprising a gate 3, a drain 5 and a substrate 7 to a high voltage decoder 102 which grounds or boosts voltage up to high voltage VP (voltage of node 110) utilizing a transistor 103 impressed with power supply voltage, a boosting circuit 101 and input signals B-D. In case of writing in, firstly impress an input signal A with high voltage (VCC) (this may be performed after input signal C) and impress another input signal C with high voltage and then impress the other signal B with high voltage. The other input signal D shall be constantly grounded. |
