| 摘要 |
PURPOSE:To reduce a hardware quantity and to operate at a high speed by sending one of an output data or a data of a memory unit to the first register in accordance with an output state of an AND gate group having a specified relation to the first register. CONSTITUTION:In a block B4 for obtaining continuously an address of 14 bit at every one clock by adding lower 4 bit to upper 10 bit, the contents A of the first register 3 of 16 bit are encoded by a priority encoder 2, and its output is converted to a negative logical output B by a decoder 1 and inputted to an AND gate group 4. Also, the i-th output Ci of the gate group 4 is made Ci=AiX Bi to the i-th input Ai of the A side and the i-th input Bi of the B side, the i- th output Ci of a selector 5 of 32 inputs and 16 outputs is made Ci=SAi+SBi against ORS of all outputs of the gate group 4, and an output of a memory unit 6 for holding upper 10 bit, and an output of the group 4 are inputted to the selector 5 as the A side and the B side, respectively. |
