发明名称 BRANCH OPTIMIZATION PROCESSING METHOD
摘要 PURPOSE:To omit a loading process by loading previously plural address constants onto plural base registers respectively and indicating the displacement from the head address of a section shown by the contents of the base register. CONSTITUTION:An object program is divided into sections 3-1, 3-2.... Then head addresses A(P1), A(P2), A(P5) and A(P8) of sections 3-1, 3-2, 3-5 and 3-8 (shown by hatching in the figure) having high possibility to be defined as branching destinations are defined as address constants respectively. These constants are first loaded and held onto registers r1-r4 respectively by a loading/multiple instruction. Then one of above-mentioned registers is indicated among branching instructions. At the same time, a displacement (d) from the head address of the section shown by the contents of the corresponding register. Therefore said sections 3-1-3-8 are regarded as a big section, and the above-mentioned loading instruction can be omitted for the branching within said big section.
申请公布号 JPS60181840(A) 申请公布日期 1985.09.17
申请号 JP19840037701 申请日期 1984.02.29
申请人 FUJITSU KK 发明人 UCHIDA MASAAKI
分类号 G06F9/32;G06F9/44;G06F9/45 主分类号 G06F9/32
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