| 摘要 |
PURPOSE:To perform the processing of a computer at a high speed and extend considerably I/O ports practically by outputting address data to select a prescribed external address and inputting input data in the selected external address to the computer with the next read instruction. CONSTITUTION:Address data nu latched in a latch circuit 103 is decoded by a write decoding circuit 201, and a latch circuit corresponding to data nu, for example, a latch circuit 231 is designated, and data P latched already in a data latch circuit 105 is latched and stored in the designated latch circuit 231. Data P is taken into the latch circuit 231 by a delay latch signal S2, and data can be latched in a stable certain time even if a latch signal S1 has a shorter cycle because of the rise of the processing speed. At the output time, a pair of output data and the external address are outputted from the computer, and data is latched in a converter circuit 100 and is stored in the external address of a virtual I/O space in buffer circuit 200. |
