发明名称 CHANNEL CONTROL SYSTEM
摘要 PURPOSE:To decrease the number of execution registers and to improve the processing capability by providing a register stack storing control information at each channel in a collection channel constituting plural channels. CONSTITUTION:The register stack 11 consists of plural registers, the control information of channel 0 is stored in a register of an address 0 and the control information of a channel 1 is stored in a register of an address 1. That is, the control information of the channel 0 is read from the stack 11 at the cycle 0 and set to the execution register 12-1. The 1st control section 13-1 references the control information of channel 0 to attain processing and updates the control information of the channel 0. The control information of the channel 1 is read from the stack 11 in the cycle 1, set to the register 12-1 and the updated control information of the channel 0 is written in the address 0 of the stack 11. Thus, the number of execution registers is decreased and the processing capability is improved.
申请公布号 JPS60176162(A) 申请公布日期 1985.09.10
申请号 JP19840033068 申请日期 1984.02.23
申请人 FUJITSU KK 发明人 SHIMIZU SEIICHI;AIZAWA TERUO;SUGIURA SATOSHI;KONDOU HIROKAZU
分类号 G06F13/12;(IPC1-7):G06F13/12 主分类号 G06F13/12
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