| 摘要 |
PURPOSE:To attain DMA transfer without intermission and to reduce the load of a processor by executing any one of DMA transfer through a buffer memory and DMA transfer through a data buffer. CONSTITUTION:An FIFO controller (memory controller) 9 is started by a designation from a processor 1 to secure a bus occupation right and control an I/O unit 5a. DMA transfer to the I/O unit 5a is continued by the existence of an FIFO memory 10b and data, and since data are read out/written between the FIFO memory 10b and memories 2, 3 in accordance with the status (full or empty) of the FIFO memory 10b, the data transfer between the I/O unit A5a and the memories 2, 3 is not intermitted. On the other hand, the DMA transfer between the I/O unit B5b and the memories 2, 3 is performed by a DMAC4 through a data buffer 6. |
