发明名称 MULTIPHASE SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To obtain a desired sampling lock by taking frame synchronism to a reception signal so as to generate a gate signal selecting plural channels in the reception signal, applying clock regeneration from the reception signal separated at each channel and synthesizing the clock to each channel. CONSTITUTION:AMI violation is used normally for frame bit detection for frame synchronism, a violation detecting circuit 11 detects it and generates a frame synchronizing signal 1. An ROM17 generates gate signals 2, 3 and 4 corresponding to channels B1, B2 and D. Since only the channel B1 is inputted to a phase synchronism circuit 14-1, a clock 5 in phase locking with the input corresponding to the channel B1 is generated. Phase synchronism circuits 14-2, 14-3 generates clocks 6, 7 in phase synchronism with the input corresponding respectively to the channels B2 and D.
申请公布号 JPS60172855(A) 申请公布日期 1985.09.06
申请号 JP19840017114 申请日期 1984.02.03
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 OKUMURA YASUYUKI;HAYASHI KAZUHIRO
分类号 H04J3/06;H04L7/04 主分类号 H04J3/06
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