| 摘要 |
<p>PURPOSE:To reduce power consumption at holding state by delaying an operating speed slower than normal state when minimum necessary operation is to be executed at the holding state. CONSTITUTION:A microcomputer outputs a signal having prescribed frequency from its oscillation circuit 1 and divides its frequency by a frequency dividing circuit 3. Both outputs CLK1, CLK2 from the circuits 1, 2 are impressed to a switching circuit 3, which is controlled by a control signal CHG from an operation control circuit 5 to output any one output selectively to a clock generator 4. The generator 4 forms a clock signal CP on the basis of the selected signal CLK and outputs the clock signal CP to respective internal circuits. When holding state is detected 6 at a time of power failure, a switching circuit 3 selects the frequency-divided output CLK2, so that the operating speed of the microcomputer is delayed by the frequency divided by the frequency dividing circuit 2.</p> |
