| 摘要 |
PURPOSE:To add and subtract numbers of data continuously at a high speed by performing the addition and subtraction, bit by bit, continuously, and making a logical shift corresponding to the weight of each bit after the addition and subtraction. CONSTITUTION:Arithmetic data held temporarily in a temporary register TMP is inputted to an addition and subtraction control circuit ID.CTL to decide on addition, subtraction, and nonoperation as to binary counters BCNT0-BCNT3. The counters BCNT0-BCNT3 perform addition and subtraction continuously and dummy registers DMYR0-DMYR3 shift the BCNTs 0-3 and convert four- bit data into eight-bit data. A full-adder F.A sums up the contents of the BCNTs 0-3 and DMYRs 0-3 successively by an accumulator ACC and supplies the final sum value to a selector SELCTOR, and the high-order and low-order data are sent out to a data bus DATABUS while divided into four bits. |
