| 摘要 |
<p>A thermal shut-down circuit that is monolithically integrated in a power BIMOS process wherein a vertical power PNP output transistor (32) comprises a P-type substrate as a collector. The circuit compensates for vertical currents injected from the P-substrate into lateral transistors. A first PNP transistor (24) has an emitter connected to a first resistor (25) and conducts a first current. A second PNP transistor (21) has an emitter connected to a second resistor (23) and conducts a second current. A third resistor (35) has one terminal coupled to the emitter of the second transistor. A fourth resistor (33) is coupled in series with an output means (32, 34, 39), the combination thereof being coupled in parallel with the second and third resistors.</p> |
