| 摘要 |
PURPOSE:To obtain an output signal of a high level by synchronizing a clock signal applied to other transfer pole driven in the same phase as the final stage transfer pole which forms a CCD and applying another clock signal which is reduced by the prescribed voltage from the low voltage side at the low voltage side. CONSTITUTION:A buried layer 2 is formed on a semiconductor substrate 1, a plurality of impurity regions 5 are formed thereon, an output gate pole 7 is provided thereon, a transfer pole 61 is provided between the adjacent regions 5, and a transfer pole 62 is provided on the adjacent pole 5. Thus, the transfer electrodes of the final stage are formed of the poles 61, 62, and when a clock signal phi2 is applied thereto, it is not directly applied, but led to the final stage clock generator 40, synchronized with a signal phi2, a clock signal phi'2 which is lower than the lower potential side in the low potential direction is generated, and applied to the electrodes 61, 62. The generator 40 is formed on N-channel depletion type MOS elements N1, N2, and N-channel enhancement type element N3, and a capacitor C. |
