| 摘要 |
A process for making stacked high voltage rectifiers includes initially doping a plurality of silicon wafers with paint-on dopants applied with an applicator that is gradually moved from the center to the outer edge of each wafer while the wafer is peripherally supported and rotated sufficiently slowly to prevent spin-off and runover of each dopant onto the reverse side of the wafer. The dopants are driven in by heating in a diffusion furnace. The same slow rotation and moving applicator technique then is used to coat only the N-doped side of the wafer with a paint-on noble metal dopant. The noble metal is driven in using a diffusion furnace at a temperature that is selected in accordance with the measured reverse recovery time of the wafer prior to noble metal diffusion. The wafers are silver coated and stacked, and a compression jig is used to exert compressive force on the stack while it is heated in a alloying furnace to a temperature sufficiently high to cause "wetting" of the silver. Thereafter the wafer stack is quickly cooled. The compressive force is programmatically varied in accordance with the stack temperature, with maximum pressure being applied as the metal "wetting" temperature is reached. Ultrasonic grinding then is used to form individual stacked junction dice from the resultant wafer stack. The dice then have leads attached, are etched to remove edge damage, and are encapsulated to form the rectifiers.
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