| 摘要 |
PURPOSE:To set the parasitic capacity at the side of a gate region to substantially zero by forming the second conductive type gate region through a hole on the first conductive layer semiconductor layer on a substrate, and forming a gate electrode having a small hole at the gate region. CONSTITUTION:An N-type GaAs layer 2 is epitaxially grown on a semi- insulating GaAs substrate 1, an Si3N4 film 3 is coated thereon, and a hole 3a is then formed. Then, a P-type impurity is thermally diffused in the layer 2 through the hole 3a to form a P<+>-type gate region 4. Then, after a Ti/Pt/Au film is coated on the entire surface, the gate electrode 5 of narrow width is formed in the hole 3. Then, with the electrode 5 and the film 3 as masks the region 4 is sand-etched to form the region 4 to the prescribed width value smaller than the width of the electrode 5. Then, holes 3b, 3c are formed at the prescribed positions of the film 3, and a source electrode 6 and a drain electrode 7 are then coated. |
