| 摘要 |
PURPOSE:To attain assuredly data reading and writing by turning a data bus to high impedance state at the periphery of a point of time generating a signal of which frequency dividing stage is 1Hz to inhibit the I/O of data. CONSTITUTION:If a control signal 2 is at the L level when a signal of 1Hz is generated from a frequency dividing stage 8, the data bus state 3 is turned to the high impedance state 3'. Namely, a data bus control signal generator 10 generates a control signal 2 to a data bus controller 12 so that a data bus 16 is turned to the high impedance state. When the 1Hz signal 1 is generated, the bus 16 is turned to the high impedance state at the periphery of the generation, so that it is prevented that data are read out/written from/in an inner counter in error. Thus, data reading/writing can be attained assuredly. |
