| 摘要 |
PURPOSE:To generate an FFT address capable of rearray an output data in the FFT operation by inverting the logic of the LSB of the FFT address counter in the final bus of the FFT. CONSTITUTION:During a path 4 which is the final bus of the FFT operation, outputs S0, S1 and S2 of a shift register 2 go to ''1'', ''1'' and ''1'' respectively, selectors 5a-5d select outputs of C1, C2 and C3 of a counter 1 and the output of an exclusive OR4, and they are outputted. Since the serial output E0 of the shift resister 2 is the logic ''1'' at this time, the output of the exclusive OR4 goes to C0 if a control input V0 is the logic ''1''. If the V0 is the logic ''0'', the output of the exclusive OR4 goes to C0. The FFT output is rearranged when V0=''1''. |
