发明名称 ERROR SIGNAL DETECTION AND CORRECTION CIRCUIT
摘要 PURPOSE:To decrease the circuit scale remarkably and to reduce power consumption of the circuit considerably by utilizing a 1H delay line for processing a luminance and a chrominance signal for the detection of an error signal. CONSTITUTION:A signal before and after the 1H delay line 301 is extracted and a luminance signal is obtained through low pass filers 302, 303 respectively. Logarithmic conversions 304, 305 are applied similarly through a subtraction circuit 306 and an exponent conversion 307, then an error detection signal 308 is obtained. In this circuit of this invention, the 1H delay line in an error signal detection circuit 309 is not used and two low pass filters and two logarithmic converters are employed. The circuit scale of the low pass filters 302, 303 and the logarithmic converting circuits 304, 305 is small and there is no problem even with increase by two. Since 1H delay line with large scale is not used, the circuit scale is far simplified more than the conventional circuit and the number of components is decreased remarkably. Thus, the power consumption of the circuit is decreased remarkably.
申请公布号 JPS60150391(A) 申请公布日期 1985.08.08
申请号 JP19840006510 申请日期 1984.01.18
申请人 MATSUSHITA DENKI SANGYO KK 发明人 MATSUOKA HIROKI;MORIMURA ATSUSHI;FUJIMOTO MAKOTO;KITAMURA YOSHINORI
分类号 H04N9/07 主分类号 H04N9/07
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