发明名称 VOLTAGE DETECTION CIRCUIT OF FEEDING CIRCUIT
摘要 <p>PURPOSE:To improve S/N of a detection circuit and the circuit system of a four- line-type output without using a large capacity high voltage resistance capacitor by attenuating the current and the amplitude value of the signal at the first detection circuit, and amplifying only the signal at the second detection circuit. CONSTITUTION:The signal and the DC voltage in terminals 2-1 and 2-2 are attenuated in accordance with the ratio between a resistance R7 and a resistance R6 by the first detection circuit 23-1 of a detection part 23. When a resistance R8 and the R6 are selected as R8<R6 in the second detection circuit 23-2, the output of the DC voltage has no gain. On the other hand, the output is amplified for the signal output. When the equation: R6/R6//R8=R7/R6 is selected here, signal components which are attenuated by the first detection circuit 23-1 are amplified by the second detection circuit 23-2 by the attenuated amount, reduced to the signal with the same voltage as that of the terminals 2-1 and 2-2, and are outputted from a terminal 20-1 of a four-line type through a feedback circuit and an HYB. Therefore, the deterioration of S/N does not occur.</p>
申请公布号 JPS60145794(A) 申请公布日期 1985.08.01
申请号 JP19840002207 申请日期 1984.01.10
申请人 FUJITSU KK 发明人 KANEKO KAZUHIRO;KATOU SEIJI
分类号 H04Q3/42;H04M19/00 主分类号 H04Q3/42
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