| 摘要 |
PURPOSE:To lock in a PLL device easily at a signal input time by providing band control circuit which can be switched to a wide band mode or a narrow band mode in accordance with the state where an output signal is locked to an input signal or not. CONSTITUTION:A device consists of a phase comparator 1 which compares the phase of the input signal with that of the output signal, a counter 2 of a phase deviation width, a frequency division ratio setter 2a which outputs the counted value with a prescribed frequency division ratio, a counter 3 which transmits the output signal on a basis of the counted value, a frequency division ratio converting circuit 4 which sets a frequency division ratio to the counter 3, a reference oscillating circuits 5, and a NOT circuit 6 which inverts the output signal and gives the inverted signal to the first counter 2 as a clock pulse. Further, a band control circuit 7 is provided which controls a time width for changing the frequency division ratio of the frequency division ratio converting circuit 4 on a basis of the phase difference between the input signal and the output signal. The circuit 7 discriminates the lock state or the non-lock state to give the output signal corresponding to the discriminated state to the converting circuit 4. |
