| 摘要 |
PURPOSE:To enable the reduction in chip area by reducing the useless region remaining in the chip periphery by a method wherein the shape of a functional block is made orthogonal-polygonal in the chip periphery. CONSTITUTION:In case of application to the CMOS logical VLSI designed by the hierarchy type layout system, the shapes of blocks 2 and 3 in the chip periphery are made orthogonal-polygonal in recess in sections closer to the center of the chip 12 in accordance with the distribution of the number of wiring pieces. In such a manner, CB/CA and WB/WA are less than 1 when the chip area and the area of an interblock wiring region in case of rectangular shapes of the blocks 2 and 3 are CA and WA, respectively; and when those in case of orthogonal shapes of the blocks 2 and 3 are CB and WB, respectively. These values are dependent on the value NW for the number of interblock wiring pieces, and the value WA/WB is about 0.9 when the value NW is 1,000. |
