| 摘要 |
PURPOSE:To display the state of an image processor without any flicker by repeating state display operation synchronously with decision making operation as to variation of a state detection signal in a stand-by period of the decision making operation. CONSTITUTION:A CPU is equipped with a ROM stored with a program for sequence control, an arithmetic circuit, an arithmetic value saving RAM, a program decoding logical circuit, etc., to generate a sequential control output for image formation successively and also output display device selection signals CT1-1, CT1-2, CR2-1, and CT2-2 and segment driving signals (a)-(d), etc., of selected display devices on time-division basis. Those display signals are outputted synchronously with the decision making operation as to the state detection signal in the stand-by period for making the decision. Therefore, display operation is controlled through the CPU, etc., without performing the sequence control independently to eliminate a flicker, thereby making a desired display of the image processing state. |
