| 摘要 |
<p>An integrated circuit development method for generating a net list called a core (logical core) composed of a net connecting ports of a block not depending on a device technology by using only connection information in the block port specification which is a result of circuit architecture study and a part of logical design document, selecting blocks as objects from the core (logical core), grouping the blocks, and using the grouped core (logical core) data. A system for concurrent development of ASIC and FPGA is constituted by a fire wall for monitoring access from the Internet, a Web server for communicating with the Web client used by a user, an authentication server for performing user authentication, a user management server for managing a user, a logical synthesis server for executing an ASIC and FPGA development program, a mail server for distributing a mail to those associated with the project, a file server for storing design information, an application server for executing an ASIC implement design program, and a monitoring server for monitoring the ASCI and FPGA development state.</p> |
