| 摘要 |
PURPOSE:To use a clock speed to any application of high and low speed with one kind of register file by switching freely the mode to any of the D type flip-flop mode or latch mode with a control pulse. CONSTITUTION:The titled device consists of two-input AND gates 1, 2, 4, 5 and two-input OR gates 3, 6, a clock pulse CP is inputted to the AND gate 1, an inverted clock pulse CP' being opposite in polarity of the pulse CP is inputted to the AND gate 2, an AND control signal CP.T between the pulse CP and the control pulse T is inputted to the AND gate 5, the OR control signal CP'+T between the pulse CP' and the inverted control pulse T' being opposite in the polarity of the pulse T is inputted to the AND gate 4 and a prescribed input signal D is inputted to the AND gate 1. Through the circuit constitution above, when the pulse T is logical 1, the operation of the D type flip-flop is conducted. On the other hand, when the pulse T is logical ''0'', the output of the OR gate 3 appears as it is as an output signal Q and the device acts like the latch mode. |
