| 摘要 |
PURPOSE:To shorten equivalently an access time per one word even if a memory element whose access time is slow is used, by reading out in parallel continuous 2K words along each axis shown by a three-dimensional logical address space. CONSTITUTION:Each line shows banks 0-3 of a memory bank, and each row is a physical address of a 4-bit portion in the bank. A number within in its drawing corresponds to a logical address. When each lower side 2-bit of logical addresses (p, y and x) is denoted as p1, p0, y1, y0, x1 and x0, respectively, the address assignment rule is bn={(a/4)+a}//4,ba=a/4, (a//4 is a surplus of the time when (a) has been divided by 4) when a bank number and a physical address of each bank are denoted as bn and ba, respectively, with respect to a=p1.2<5>+ p02<4>+y1.2<3>+y1.2<2>+x1.21+x02<0>, and as a result, as for four words continued in the three axes direction of the three-dimensional space, their bank numbers are different from each other, therefore, the access can be executed in parallel. |
