| 摘要 |
<p>PURPOSE:To extract a stable clock signal component by using an integration circuit for a timing extracting circuit so as to apply integration thereby arranging the phase of a fundamental frequency f0 component and a 1/2 f0 component in a signal receiver of tri-state value where a limiter amplifier is used for a main signal system so as to make the input amplitude of a discrimination circuit constant. CONSTITUTION:A common limiter amplifier 21 is provided to a pre-stage of both a discrimination circuit 13 and a timing extracting circuit 14, and an integration circuit 22 is inserted to the 1st stage of the timing extracting circuit 14. When an input signal level is high, a signal with a waveform shown in Fig. (top) is inputted to the input side of the timing extracting circuit 14. This signal is integrated by an integration circuit 22 and its output waveform is as shown in Fig. (middle). The output of the integration circuit 22 is subject to full wave rectification by a full wave rectifier circuit 17 and its full wave rectified waveform is as shown in Fig. (bottom). That is, the waveform shown in Fig. (bottom) consists of two waveforms whose basic repetitive frequencies are f0 and f0/2 with matched phase, and a stable clock signal component is extracted by leading them to a tank circuit 18 having the tuning frequency of f0.</p> |
