发明名称 |
1-CHIP DIGITAL SIGNAL PROCESSOR |
摘要 |
<p>PURPOSE:To obtain a chip for evaluation of a program proper in size by applying an address, data and a write signal through the 1st, 2nd and 3rd terminals respectively and setting a coefficient to a coefficient memory from outside. CONSTITUTION:A terminal 20 is set at logic 1 in a program development mode. Then a 3-state buffer 18 is turned off and the side (b) of the input of a multiplexer 14 is selected. Thus an address can be given to a coefficient memory 11 from outside via a terminal 12. While a 3-state buffer 19 is turned on and data can be given to the memory 11 from outside via a terminal 17. Under such conditions, a write pulse is applied through a terminal 21 to write the data to the memory 11. Then the terminal 20 is set at logic 0 and the output of a program counter 10 is outputted to the outside of a chip through a terminal 12 via a buffer 20. Then an access is given to a program memory set outside, and the output of the program memory is supplied to an instruction register 15 through the terminal 17.</p> |
申请公布号 |
JPS60129882(A) |
申请公布日期 |
1985.07.11 |
申请号 |
JP19830238198 |
申请日期 |
1983.12.16 |
申请人 |
MATSUSHITA DENKI SANGYO KK |
发明人 |
UEDA KATSUHIKO;KIYOHARA TOKUZOU;SAKAO TAKASHI |
分类号 |
G06F15/78;G06F17/10;H03H17/02 |
主分类号 |
G06F15/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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