WATCH-DOG TIMER CIRCUIT

摘要

Watch-Dog Timer Circuit A watch-dog timer monitor for the control system of a power plant including a pulse monitor which measures the length of time between successive control pulses from an output port of a computer. In the event that any control pulses exceeds the preselected time interval, the pulse monitor sends a disable signal through a latch to the buffers in the path of the control signals. The buffers instantaneously transition to a blocked condition preventing any subsequent control pulses from reaching the control system of the power plant. A reset button is toggled to reset an initializer which restarts the program in the computer. A start-up delay is also provided to insure that no spurious control pulses reach the control system of the power plant during a warm-up period when the digital logic circuits are settling out.