| 摘要 |
<p>PURPOSE:To shorten the A/D conversion time of multi-input signals by forming two sample holding circuits and switching them alternately to use them. CONSTITUTION:Multi-input signals S11-S1n are swtiched by a multiplexer 11, arrayed as time series signals and outputted as a signal S0. The signal S0 is inputted two sample holding circuits 17, 21 through a buffer 13 and an amplifier 15, but since a switching control signal SC2 is applied to the sample holding circuit 21 through an inverter 24, one sample holding circuit is kept at the holding status during the period that the other is in sampling. Namely, the other sample holding circuit is sampling the succeeding signal during the period one sample holding circuit is applied to the proceding holding value to the succeeding A/D converter 29 through an alteration switch 25 and a buffer 27, so that a time corresponding to the sample processing time can be shortened and the A/D conversion time of the multiinput signals can be shortened.</p> |
