| 摘要 |
PURPOSE:To actuate a memory circuit with a mean working current of a satisfactorily small level by latching the logical level of a word line and driving the word line in response to the latched logical level. CONSTITUTION:When the writing to a memory cell 118 is ended, a writing end detecting part 113 delays a word line clock signal phiX and produces a writing end detecting signal phiW'. When a dummy word signal line WD has a rise, a node point N14 is set at a low level. Then the signal phiW' has a fall and a clock generating part 107 works to give a fall to a precharge clock signal phiP and the signal phiX respectively. While a rise is given to a pull-up clock signal phiPU and a latch clock signal phiL respectively. A word line is set at a high level only in a fixed period to minimize the level reduction of a non-selection bit line at the side line of the ''0'' information. This attains a big reduction of the precharge current of a bit line. |
