发明名称 |
Addressable buffer circuit with address incrementer independently clocked by host computer and external storage device controller |
摘要 |
A direct buffer access circuit provides a buffer memory for use with a host central processing unit and a peripheral controller for controlling an external data storage device such as a disk or tape drive. The buffer is connected so that both the host and the controller have direct access to the buffer. The host can thus transfer data to the buffer at its own data rate independently of the transfer rate of the controller. The buffer may include either a random access memory which is addressed by a counter, or a first-in/first-out memory. The buffer is controlled by signals received from either the host or the controller.
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申请公布号 |
US4527233(A) |
申请公布日期 |
1985.07.02 |
申请号 |
US19820401700 |
申请日期 |
1982.07.26 |
申请人 |
AMBROSIUS, III, WILLIAM H.;CHUNG, RANDALL |
发明人 |
AMBROSIUS, III, WILLIAM H.;CHUNG, RANDALL |
分类号 |
G06F5/10;(IPC1-7):G06F13/00;G06F13/04;G06F15/16 |
主分类号 |
G06F5/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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