| 摘要 |
PURPOSE:To shorten the memory writing time of a processor, by sending out data of the same contents and continuous memory addresses at once from the processor to a data transfer controlling device, when said data are written in the continuous memory addresses. CONSTITUTION:A data register 10, address register 11 which is capable of update by (+1), and subtracting by (-1) register 16 which performs count-up control on the address register 11 are installed to a data transfer controlling device 2. The subtraction counter 16 once stores the number of continuous addresses and performs (-1) subtraction whenever memory writing is performed. A flip- flop 26 controls the output of a memory writing request signal. Each register 10, 11, and 16 decodes a memory writing request from a common bus 3 by means of a decoder 25 and writing is simultaneously performed synchronously to a timing pulse 30. The number of continuous addresses is set in the subtraction counter 16 from a signal line 18 and subtraction by (-1) is performed at every memory transfer. This operation is repeated until all the outputs are reduced to zero. |
