| 摘要 |
PURPOSE:To eliminate a restriction against the reduction of pattern size, and to manufacture a semiconductor device, the degree of integration thereof is improved, by making the density of a pattern for a wiring body in plural layers equal and preventing trouble due to positional displacement without particularly forming a compensation diffusion process. CONSTITUTION:Regarding source and drain regions 8 in an N channel FET, windows are bored to a PSG film 11, and implanted impurity ions are activated to form impurity diffusion layers in required depth while thermally treating the surface of the PSG film 11 for smoothing. First layer wiring bodies 22, 22A are formed, and windows reaching to source and drain regions 9 and a gate electrode 7P in a P channel FET are bored to the PSG film 11. A second PSG film 23 as an inter-layer insulating film is shaped, and a window is bored in order to connect a second layer wiring body regarding the source and drain regions 9 and the gate electrode 7P in the P channel FET and a connecting region 22A with the first layer wiring bodies. The second layer wiring body 24 is formed. |
