发明名称 SEMICONDUCTOR MEMORY CIRCUIT
摘要 PURPOSE:To prevent the generation of a malfunction even to a small amount of noises by constituting a writing amplifier with the 1st inverter to which an input signal is impressed and the 2nd inverter which uses the output of the 1st inverter as an input and connecting a transistor which is turned on in a chip non-selection mode between the output terminal of each inverter and a power supply terminal. CONSTITUTION:In a chip non-selection mode C'E', an r/w is set at a level VDD and FETQ38 and Q42 set at the drive side of each inverter of a level conversion circuit 14 are turned on to prescribe forcibly the output of each inverter at a level GND. Both outputs din and din' of a writing amplifier are set at a level VDD respectively. Then a chip selection signal CE is set at a level VDD, and the level of the r/w signal is set at GND when a write signal is impressed. Thus FETQ38 and Q42 are turned off, and the output din is set at VDD with the other output din' set at GND respectively. Then a writing action is carried out to a memory cell. While the signal r/w is set at VDD in a read mode of a memory circuit, i.e., when a read signal r'/w' is set at GND. The output state has no change and both outputs din and din' are set at VDD.
申请公布号 JPS60121596(A) 申请公布日期 1985.06.29
申请号 JP19840236605 申请日期 1984.11.12
申请人 HITACHI SEISAKUSHO KK 发明人 SATOU TAKASHI
分类号 G11C11/409;G11C11/34;G11C11/417;(IPC1-7):G11C11/34 主分类号 G11C11/409
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