| 摘要 |
PURPOSE:To diffuse impurity having a large diffusion coefficient to a junction boundary surface in low concentration, and to realize the increase of the withstanding voltage of an element by using a gate electrode twice in a self-alignment manner when the impurity is diffused twice in high concentration and low concentration. CONSTITUTION:Oxide films 5-1, 5-2 are formed on a semiconductor substrate 1 through thermal oxidation. Polycrystalline silicon containing phosphorus in high concentration is deposited on the oxide films 5-1, 5-2, and a gate insulating film 2 and a gate electrode 3 are formed through a photo-resist processing technique. Phosphorus ions are implanted at predetermined acceleration voltage and in a fixed quantity, and impurity regions 4-1, 4-2 are formed through heat treatment. An oxide film 5-3 is shaped around the gate electrode 3 because silicon is contained in high concentration at that time. Arsenic ions are implanted at predetermined acceleration voltage and in a fixed quantity, and diffusion layers 6-1, 6-2 are formed through heat treatment. An impurity having a large diffusion coefficient is diffused to a junction boundary surface in low concentration, thus increasing the withstanding voltage of an MOS type FET. |
