| 摘要 |
PURPOSE:To obtain a frequency divider with setting in a simple constitution by adding an inverter as well as two transistors which define the setting timing at a clock fall time point and set forcibly both an internal state and an output terminal state. CONSTITUTION:When a set terminal is set at a high level synchronously with the fall of a clock CL, transistors TR102 and 103 are turned on. An output terminal 13 is set at a high level and at the same time an internal state VB, i.e., the state of a terminal 12 is set at a high level. Both the internal state and the output terminal state are set continuously despite the discontinuation of supply of the clock CL since the set state is set at an earth potential, i.e., at a high level. When the set level is set at a low (negative) level, both TR102 and 103 are turned off to start a normal dividing action. Therefore the internal state has no change even if the clock supply is stopped with the specific timing. Thus a setting action accordant with a logical fast/slow action is possible. |
