| 摘要 |
<p>Semiconductor integrated circuit which has: first and second semiconductor regions which are formed in pillarlike projections provided on a semiconductor substrate or a semiconductor layer provided on an insulating substrate, the semiconductor regions opposing each other across an insulating region; a p-channel FET provided in the first semiconductor region and an n-channel FET provided in the second semiconductor region, each of the FETs having source and drain regions at the upper and bottom portions respectively of the corresponding semiconductor region and a gate electrode at a side portion of the semiconductor region. Also disclosed is a semiconductor integrated circuit in which the insulating region between the semiconductor regions in the shape of a pillarlike projection is employed as a gate electrode and a gate insulating film.</p> |
