| 摘要 |
<p>1. A field effect transistor having a vertical structure and comprising, on a substrate (13) made of semiconductor material, at least one first layer (14) of a high doping rate, a second layer (15) of a low doping rate and a third layer (16) of a high doping rate, the first layer (14) and the third layer (16) constituting the lower and upper access zones, called source and drain, the contact metallisations (17, 18) of which are respectively supported by the rear surface of the substrate (13) and by the third layer (16), the third and the second layers (16, 15) constituting a mesa, the gate electrode device (19) being deposited on the slopes of the mesa and modulating the channel in the second layer (15), characterized in that in order to suppress the parasitic source and drain access zones, the thickness of the second layer (15) in which the transistor channel is made up, is entirely controlled by the gate metallisation (19) which is at least as long (h) as the thickness of the second layer (15) and which in part (c) covers at least the third layer (16), and that said metallisation (19) is separated from the third layer (16) by a layer of a dielectric material (21) having an electrical leak and being deposited on the slopes of the mesa.</p> |
