发明名称 |
MEMORY READOUT CONTROL SYSTEM. |
摘要 |
<p>A high-speed memory (4) is constructed so that it is provided with at least a first data-storage region (4a) which is accessed by a processor (1) and a second data-storage region (4b) into which data in a low-speed memory (5) is transferred and stored. The processor (1) reads data out of the first data-storage region (4a) of the high-speed memory (4), then transfers the data in the second data-storage region (4b) of the high-speed memory (4) into the first data-storage region (4a), and also accesses the low-speed memory (5) to transfer data therein into the second data-storage region (4b) of the high-speed memory, so that the processor can continuously read out data regardless of any access to the low-speed memory.</p> |
申请公布号 |
EP0144432(A1) |
申请公布日期 |
1985.06.19 |
申请号 |
EP19840901404 |
申请日期 |
1984.03.30 |
申请人 |
FANUC LTD |
发明人 |
SAKAKIBARA, SHINSUKE;TACHIBANA, MITSUO |
分类号 |
G05B19/408;G06F5/06;G06F12/08;G06F13/28;(IPC1-7):G06F13/00 |
主分类号 |
G05B19/408 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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