| 摘要 |
PURPOSE:To contrive the reduction in feedback capacitance, improvememt of gain, and improvement of high frequency characteristics due to the decrease in noise index by isolation-shielding the input-output electrodes of the gate and drain by a source electrode of the ground electrode by a method wherein a pair of leads projected out to four direction from the peripheral wall of a resin-sealed type package are joined in the package to an integral structure, and a gate lead is arranged on its one side and a drain lead on the other side. CONSTITUTION:The leads 5 project out to four directions from the peripheral wall of the package 4 of a single gate FET high frequency planar transistor. A pair of the source leads 6 and 9 come to an integral body in the package and fix a chip 11 at the fixing part 10. Because of the projections 13 of grooves 12 for water infiltration prevention, the source leads and the resin package do not slide from each other. On the other hand, the inner ends of the gate lead 7 and the drain lead 8 are positioned in the neighborhood of the chip-fixing part 10 of the source leads, and covered with the resin package. Each electrode of the chip is electrically connected to the inner end of the each lead by means of wires 14. |
