| 摘要 |
PURPOSE:To cancel a feedthrough by connecting a dummy inverter to the output of a final inverter at a side where no delay inverter is connected, and equalizing the load capacity of the final-stage inverter which generates each clock signal. CONSTITUTION:An inverter 1 inverts a clock signal CLK. The output of an NAND circuit 2 is passed through inverters 3 and 4 to generate a clock signal -phi1, and also inverted by an inverter 5 to generate a clock signal phi1. Then, dummy inverters 12 and 13 are connected to inverters 4 and 11 on the side where delay inverters 6 and 9 are not connected. Consequently, the gate capacities of inverters 12 and 13 are connected as load capacities to the inverters 4 and 11 to equalize the load capacities between the inverters 4 and 5, and 8 and 11. Consequently, the rising time of the clock signal is made coincident with the falling time. |
