| 摘要 |
PURPOSE:To decrease a test time without inflicting hindrance to normal memory operation by addressing individually a memory chip at the operating mode, and addressing simultaneously plural memory chips to output the data from the said chips in common at the test mode. CONSTITUTION:An address circuit testing plural memory chips at the same time, an output control means and a mode switching means are provided. At the test mode, in bringing the level of a switch signal to a mode switching terminal MC to ''L'', a decoder 21 is disconnected from memory chips 26-1-264 and tri-state TTLs 27-30 produce no output at all. In this state, a test pattern from a Din terminal is fed to each memory chip at the same time, each memory chip is addressed at the same time by addresses A0-An and a chip selection signal *CS2 and data read at the same time are fed to an EX-NOR circuit 31. The output is fed to an NAND circuit 32 together with an output of the chip 26-1. Thus, an MPX35 is outputted only when each chip supplies an output at the same time. At the operating mode, the switching signal is brought into ''H'' level to address one of the memory chips by addresses An+1 and An+2.
|
