发明名称 CODE ERROR DETECTING CIRCUIT
摘要 PURPOSE:To allow the use of a code error detecting circuit even when the bit rate of a transmit signal is 100Mb/sec by providing a means which outputs a limit signal when the counted value of an up/down counter exceeds a specific range. CONSTITUTION:When an optical transmission system perform nBmB conversion so that a running digital sum (RDS) is within the specific range, the running digital sum is calculated, and a decision circuit decides that a code error occurs when the sum exceeds the specific range. This circuit consists of the U/D counter 6 which follows up the bit rate of the transmit signal even above 100Mb/sec a selector 7, an FF8, NOR circuits 9 and 10, and OR circuits 11 and 12, so this circuit is usable as the code error detecting circuit even when the bit rate of input data attains to 100Mb/sec.
申请公布号 JPS60107922(A) 申请公布日期 1985.06.13
申请号 JP19830215188 申请日期 1983.11.16
申请人 FUJITSU KK 发明人 YAMAUCHI TOSHIYUKI;HANABATAKE TOSHIO;WADA NORIYUKI
分类号 H03M13/00;G06F11/00;H03M5/14;H03M7/14 主分类号 H03M13/00
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