发明名称 MULTIPROCESSOR CONTROL SYSTEM
摘要 PURPOSE:To decrease the reduction of executing speed of the system due to a loop of a test and set instruction by allowing an unlock instruction to output an unlock signal. CONSTITUTION:A processor P0 executes the operation of a common resource according to a program and when the operation is finished, the unlock instruction is executed. The operand of the unlock instruction is the same as that of a GATE locked by a lock instruction. An address of the GATE is calculated at first in the unlock instruction and the right of use of a common bus is obtained from a bus arbitor, then the calculated address is outputted to an address bus AB, data of all bit ''0'' are outputted to a data bus DB and a write signal is outputted to a control signal bus CB respectively so as to write ''0'' to all bits of the GATE. After the unlock signal ULS is outputted, the right of use of the common bus is given up and then the instruction is finished. Thus, the lock and the release of lock of the common resource are performed in this way.
申请公布号 JPS60107170(A) 申请公布日期 1985.06.12
申请号 JP19830214534 申请日期 1983.11.15
申请人 NIPPON DENKI KK 发明人 NANBA SHINJI
分类号 G06F15/16;G06F9/46;G06F9/52;G06F12/00;G06F15/167;G06F15/177 主分类号 G06F15/16
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