发明名称 SLOT LINE BALANCED FREQUENCY MULTIPLIER CIRCUIT
摘要 PURPOSE:To obtain a multiplication gain in a high frequency band by performing opposite-phase distribution with circuit constitution which does not any factor limiting an applicable frequency range, and performing balanced frequency multiplication. CONSTITUTION:The input signal of an input port 1 is applied to gate electrodes 11 and 12 of FETs 8 and 9 through an input line 43, but a conductor base body 15 connected to source electrodes 21 and 22 is at the middle point between the potentials of both-side conductor layers 44 and 45 constituting a line 43, so input signals applied to the electrodes 11 and 12 are opposite in phase. Therefore, the opposite-phase distribution is carried out without any factor which limits the applicable range of frequency. Further, output signals appearing at electrodes of the FETs 8 and are applied to slot lines 46 and 47. The external conductor layer 52 of the lines 46 and 47 is connected to the base body 15 through a short-circuit conductor layer 53 and at the same potential with the electrodes 21 and 22, so multiplied waves generated between sources and drains are converted efficiently to the lines 46 and 47; and output signals of even order are opposite in phase and signals of odd order are in phase, so that only even-multiplied waves are coupled with a microstrip line 51 and outputted from an output port 37.
申请公布号 JPS60106207(A) 申请公布日期 1985.06.11
申请号 JP19830214451 申请日期 1983.11.14
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 OGAWA HIROTSUGU;HIROTA TETSUO
分类号 H03B19/14;(IPC1-7):H03B19/14 主分类号 H03B19/14
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