| 摘要 |
<p>PURPOSE:To eliminate the necessity of the filter arithmetic by using superposedly the inserted filter used with a ROM in clock synchronization in the demodulation, etc. of digital data transmission. CONSTITUTION:A multi-value digital signal sampled at a period Ts is inputted to a multi-value digital inserted filter 8 and the inserted waveform is outputted with the high speed waveform. The inserted waveform is sampled by the first sample 1 sampled by the zero phase of the clock signal and the second sample 2 sampled by a pi phase. By inputting both sample values to the timing error detecting device composed of an discriminator 3, a differentiation device 4, and a multiplier, a control signal is obtained. Based upon the control signal, so that the sample value of the sample 1 can be the optimum sample phase, a timing control circuit 6 to output a data sample timing signal 105 and a zero cross detecting timing signal 106 is provided.</p> |
