| 摘要 |
PURPOSE:To allow the addressing to cope with the transmission system of an optional scale by detecting a serivce bit as auxiliary information added to a frame synchronising signal to detect the address state. CONSTITUTION:When a digital signal including a word synchronizing signal (WS) added to a series of each word, a frame synchronizing signal (FS) added to the WS and a service bit (SB) added to each of the FS is inputted, the SB is impressed to a latch circuit 2 and a detection circuit 5, and the WS, FS are impressed to detection circuits 3, 4 respectively. The circuit 3 detects sequentially the WS, gives it to a counter 6 as a clock signal and the signal is counted. The circuit 4 detects the FS arranged at the head of each frame and drives the circuit 5. The circuit 5 detects the SB added to the FS, and when the SB is a start pattern, the counter 6 is reset and the output of the counter 6 is inputted to a coincidence circuit 7. The circuit 7 compares it with the own address 8, and when they are coincident, the own SB is outputted to a microcomputer 9 from the circuit 2.
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