发明名称 TWO-STAGE SAMPLE/HOLD CIRCUIT
摘要 PURPOSE:To reduce power consumption through simple constitution by driving the current source of a buffer circuit only at the timing of plural sampling pulses. CONSTITUTION:Depletion type FETs 111 and 131 are used and a sampling pulse is supplied to the gate of an enhancement type FET141. Further, a depletion type FET151 is used and a sampling pulse phiSP' is supplied to the gate of an enhancement type FET191 provided in parallel to the FET141. Other stages are constituted similarly. Then, the FETs 141 and 191 are off while no sampling pulse is supplied, and no current flows. When a sampling pulse is supplied, the FETs 111, 131, and 151 transfer a display signal efficiently and the FETs 141 and 191 operate in a saturation area and serves as constant current sources. Consequently, the current value in sampling is equalized to that in reading operation and the pulses phiSP' and phiSP are used as they are.
申请公布号 JPS60101799(A) 申请公布日期 1985.06.05
申请号 JP19830209489 申请日期 1983.11.08
申请人 SONY KK 发明人 SONEDA MITSUO;HAYASHI YUUJI
分类号 H03M9/00;G11C27/02 主分类号 H03M9/00
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