发明名称 FREQUENCY ADDER AND SUBTRACTER
摘要 PURPOSE:To eliminate an error in setting a circuit constant and to add and subtract a high-precision frequency signal by composing all circuits of digital elements. CONSTITUTION:An oscillator 5 generates a reference frequency signal Fs, a frequency divider 6 divides its oscillation frequency Fs by N0, and counters 8 and 9 count pulses of input frequency signals F1 and F2 respectively for constant N0/Fs sec their outputs N1 and N2 are added digitally by an adder 10, whose addition output is inputted as a frequency division ratio to a frequency divider 12 to divide said reference frequency signal Fs. Pulses of this frequency-divided output Fs/(N1+N2) are counted by a counter 12 for N0/Fs sec and the counted data is held by a latch circuit 13. This data is used by a frequency divider 14 to divide the frequency of the reference frequency signal Fs, obtaining the added frequency signal.
申请公布号 JPS60100225(A) 申请公布日期 1985.06.04
申请号 JP19830207896 申请日期 1983.11.04
申请人 RICOH KK 发明人 KIGUCHI HIROYUKI
分类号 G06F7/62;G06F7/60;G06F7/68 主分类号 G06F7/62
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