发明名称 METHOD FOR PROTECTING TRI-STATE GATE
摘要 PURPOSE:To prevent destruction of a tri-state gate at the time of conducting electricity by providing a decoder circuit between enable logic and a tri-state gate. CONSTITUTION:Enable logic 1-1-1-3 are respectively connected to inputs C, B, and A of a decoder 2, outputs Y4, Y2 and Y1 of the decoder 2 are respectively connected to an enable input of the tri-state gates 3-1-3-3. The outputs of the tri-state gates 3-1-3-3 are connected in common to internal bus. The decoder 2 prevents destruction of the entire tri-state gate 3-1-3-3 which are connected to the common internal bus line at the time of conducting electricity under high impedance conditions or by enabling only one tri-state gate to prevent destruction of the tri-state gate 3-1-3-3 which threaten to occur at the time of conducting electricity.
申请公布号 JPS60100247(A) 申请公布日期 1985.06.04
申请号 JP19830207378 申请日期 1983.11.07
申请人 HITACHI SEISAKUSHO KK;HITACHI MAIKURO COMPUTER ENGINEERING KK 发明人 BANDOU HIROAKI;TAKAHASHI SHIGEKAZU
分类号 G06F13/00;(IPC1-7):G06F13/00 主分类号 G06F13/00
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