| 摘要 |
PURPOSE:To obtain a wiring fitted to integration by forming each electrode for a collector, a base and an emitter on the same flat plane in a hetero-junction bipolar transistor using a compound semiconductor. CONSTITUTION:An N<+> type GaAs layer 12 and an N<-> type GaAs layer 13 are laminated on a GaAs substrate 11 and grown in an epitaxial manner, and the laminate is isolated insularly by an element isolation region 14a intruding to the substrate 11. The same isolation region 14b reaching to the layer 12 is formed in a region surrounded by an island, and the layer 13 positioned between the region 14b and the region 14a is used as a collector region. An N<+> type collector contact region 15 is shaped to the layer 12 between the region 14b and another region 14a through ion implantation, and unfied with the layer 13, and a P<+> type GaAs layer 16 and an N<-> type GaAlAs layer 17 are laminated on the whole surface and grown in an epitaxial manner. The layers 16 and 17 are left only on the collector region and others are removed through etching, an N<+> type emitter region 19 and a P<+> type base contact region 20 are formed in the layer 12, and electrodes 21-23 are each shaped in the regions 15, 19, 20. |
