| 摘要 |
Method for the operation of a couple (MB3a, MB3b) of memory blocks working in parallel. At least one processor (BP, IOC) reads and writes information into the two blocks (MB3a, MB3b) in a normal operating time with read-write operation, the first block (MB3) respectively storing under one of its addresses the same information as the second block (MB3b) does under the same address. The first and second blocks (MB3a, MB3b) can be switched off in order to block access in a special operating time, at least during reading from said switched-off block (MB3b), in which case only the first block (MB3a) is operated completely in read-write operation. During the special operating time, an address generator (e.g. in IOC1) can systematically produce all the addresses of the blocks (MB3) sequentially, at least in stages. At the end of the special operating time, upon transition to the normal operating time, for the purpose of updating the information to be stored in the switched-off block (MB3b) during writing into the first block (MB3a), the same information is written into the second block under the same address. The address generator gradually supplies all the addresses of the pair (MB3) of blocks, for example during a pause in the read-write operation, the information read out in this process from the first block (MB3a) being written into the second block (MB3b) under the same address. Thereafter, both blocks (MB3) can once again be operated in parallel. <IMAGE> |
